Category Archives: ECET 380 (recent)

ECET 380 Week 5 Lab Code Division Multiple Access A 3G Cellular Multiple Access Scheme recent

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ECET 380 Week 5 Lab Code Division Multiple Access A 3G Cellular Multiple Access Scheme recent

Code Division Multiple Access A 3G Cellular Multiple Access Scheme 

I. OBJECTIVES

1. Use the TIMS modeling system to generate a CDMA signal.
2. Detect the messages transmitted in the CDMA signal in a noiseless channel.
3. Add degradation in the form of noise to a CDMA signal.
4. Study the effects of noise on a CDMA signal.

II. PARTS LIST
Equipment:
IBM PC or Compatible with Windows 2000 or Higher
Software:
TutorTIMS – Version 2.0 Advanced

The following TIMS modules will be required for the lab. Read about the modules required for the particular lab section before proceeding:

1. Sequence Generator
2. Multiple Sequence Source
3. Master Signals
4. Adder
5. Digital Utilities
6. Quadrature  Utilities
7. Noise Generator
8. CDMA Decoder
9. Error Counting Utilities (Error Counter)
10. Phase Shifter

III. INTRODUCTION
The scarcity of the available spectrum and the explosive growth in the popularity of wireless communications devices absolutely imposes the need for the sharing of the available bandwidth among wireless applications subscribers.  A number of multiple access schemes exist to meet this demand, each with its own merits and demerits, including:
• FDMA – Frequency Division Multiple Access: Deployed in the now mostly outdated 1G standards, this scheme was highly bandwidth inefficient.
• TDMA – Time Division Multiple Access:  More spectrally efficient than FDMA and still in operation in 2G standards such as GSM, which is still widely deployed in many countries around the world.  TDMA is also the multiple access scheme of choice for most of the wireless data-centric standards.
• CDMA – Code Division Multiple Access: This is the access scheme of choice for 3G and other evolving standards such as CDMA 2000 and W-CDMA.  This scheme, when combined with spread spectrum, imparts certain advantages, as we shall observe in this lab. It should be noted that the combination of the multiple access scheme and the duplexing method (TDD, FDD) used in an application is known the “air interface” method for that particular application. 

CDMA

In the CDMA scheme, each subscriber is assigned a unique code which is as different from that assigned to all other subscribers as possible.  This setup allows the subscribers to use the same allotted spectrum, say in a particular cellular communications cell, with minimal interference to one another.
In the CDMA scheme, there is no need to divide the spectrum into tiny bands, as in FDMA, and subscribers do not have to take turns occupying a relatively large available bandwidth, as in TDMA.  This means that in CDMA applications, a relatively large bandwidth is occupied all of the time when allotted to a subscriber.
One can thus see why CDMA is the scheme of choice for the 3G and beyond cellular standards.  Little frequency planning is needed.  It also has a large occupied bandwidth, without the latency issues that arise from time division sharing.  This all leads to the possibility of supporting very high data rates, when combined with other PHY layer schemes such as modulation and compression.  In addition, the technique of spread spectrum, which is bandwidth driven, can be exploited.  This helps mitigate channel-imposed degradations, such as multipath fading.
Table 1 shows CDMA deployment in 2G and beyond cellular standards with 2G GSM shown for comparison:

Introduction to OFDM Generation
IV. OBJECTIVES
1. Introduce the student to the underlying theory of operation of Orthogonal Frequency Division Multiplexing (OFDM).
2. Learn to use TIMS modules to implement an OFDM generator scheme.
3. Generate and analyze OFDM waveforms.

V. PARTS LIST
Equipment:
IBM PC or Compatible with Windows 2000 or Higher
Software:
TutorTIMS – Version 2.0 Advanced

The following TIMS modules will be required for the lab. Read about the modules required for the particular lab section before proceeding:

11. Sequence Generator
12. Multiplier
13. M-Level Encoder
14. Phase Shifter
15. Master Signals
16. Adder
17. Tunable LPF
18. 100 KHz Channel Filters
19. Decision Maker

VI. INTRODUCTION

OFDM (Orthogonal Frequency Division Multiplexing) is a combination of modulation and multiplexing, and more specifically, is a special case of Frequency Division Multiplexing (FDM), as the name implies.  

A single main data stream is split into many lower rate data streams (multiplexing).  Each of these streams is then individually modulated onto a separate sub-carrier (modulation) and finally recombined into a single composite OFDM signal to be transmitted.

The addition of a cyclic prefix is also an important part of OFDM, however, this feature will be discussed but not implemented in this introductory experiment.  The coding blocks will not be covered in detail within this experiment. 

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ECET 380 Week 7 iLab Frequency Shift Keying A Bluetooth Modulation Lab recent

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ECET 380 Week 7 iLab Frequency Shift Keying A Bluetooth Modulation Lab recent

Summary (two sentences) (2pts):

The purpose of this lab was to use Tutor TIMS to implement and learn about Orthogonal Frequency Division Multiplexing(OFDM). In addidion, Tutor TIMS was used to generate an OFDM signal.
I.OBJECTIVES
Introduce the student to the underlying theory of operation of Orthogonal Frequency Division Multiplexing (OFDM).
Learn to use TIMS modules to implement an OFDM generator scheme.
Generate and analyze OFDM waveforms.
II. PARTS LIST
Equipment:
IBM PC or Compatible with Windows 2000 or Higher
Software:
TutorTIMS – Version 2.0 Advanced
The following TIMS modules will be required for the lab. Read about the modules required for the particular lab section before proceeding:
1.Sequence Generator
2.Multiplier
3.M-Level Encoder
4.Phase Shifter
5.Master Signals
6.Adder
7.Tunable LPF
8.100 KHz Channel Filters
9.Decision Maker
III.INTRODUCTION
OFDM (Orthogonal Frequency Division Multiplexing) is a combination of modulation and multiplexing, and more specifically, is a special case of Frequency Division Multiplexing (FDM), as the name implies.
A single main data stream is split into many lower rate data streams (multiplexing). Each of these streams is then individually modulated onto a separate sub-carrier (modulation) and finally recombined into a single composite OFDM signal to be transmitted.
The addition of a cyclic prefix is also an important part of OFDM, however, this feature will be discussed but not implemented in this introductory experiment. The coding blocks will not be covered in detail within this experiment.

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ECET 105 Week 7 iLab Add-Subtractor using Flip-Flops recent

ECET 105 Week 7 iLab Add-Subtractor using Flip-Flops recent

I.         OBJECTIVES
To test the operation of a 74LS74 D flip-flop and compare the operation with the predicted behavior
To test the operation of a 74LS112 J-K flip-flop and compare the operation with the predicted behavior
To measure propagation delays of a 74LS112 J-K flip-flop
To build and test an enhanced adder-subtractor
II.       PARTS LIST
Equipment:
IBM PC or Compatible with Windows 2000 or Higher

Quartus II Design Software—Version 9.1
Frequency Generator
Oscilloscope
Parts:
2 – 330 Ω resistors, ¼ W                              2 – Red LEDs
1 – 74LS74 dual D flip-flop                          1 – Green LED
1 – 74LS112 dual J-K flip-flop                     1 – SPDT Switch, DIP configuration
1 – eSOC III FPGA Board

III.         PROCEDURE
A.  Test the 74LS74 D Flip-Flop

Build the D flip-flop circuit shown in Figure 7.1. The LEDs are wired as active-LOW since the flip-flop can supply more current in a low state than in a high state. This means that the green LED is on when is HIGH and the red LED indicates Q is HIGH. Remember to attach VCC to pin 14 and ground to pin 7.
Using the circuit, verify that the operation follows the truth table for this device.

What happens when both and are set low?
Build the J-K flip-flop circuit shown in Figure 7.2. Remember to attach VCC to pin 16 and ground to pin 8.
Using the circuit, verify that the operation follows the truth table for this device.

Increase the pulse generator output to 1.0 MHz. Set the switches so that all of the flip-flop inputs are high and remove the LEDs and resistors. Using the oscilloscope, measure the propagation times for the Q output from the active clock edge. Record the value below.
Using Quartus II, modify the circuit from Lab 5 as shown in Figure 7.3 by adding three 7474 D-flip-flip chips. Note that a clear function has been added and that the flip-flop presets are inactive since they are tied to +5V (labeled VCC).
Perform a simulation to verify the correct operation of the circuit. Note that in this case, the CLOCK signal is not a periodic signal; the CLOCK signal is a discrete signal occurring on a switch closure.
Assign pins to the inputs and outputs. Use the DIP switches for your inputs (0-3 for A, 8-11 for B, 7 for CLEAR, 15 for ADDSUB), one of the debounced pushbuttons for CLOCK and the red LEDs for outputs (RD0-4).
Download you program to the eSOC III board and test the operation of the circuit.

Photograph your final circuit for submission (online) or demonstrate your circuit to your professor (onsite or blended).
Why is the condition when both and are LOW considered illegal?
How do the values you measured for tPHL and tPLH compare with values specified in the 74LS112 data sheet? You may need to go online to find this value.
Why were the LEDs removed before making the propagation delay measurements?

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ECET 105 Week 7 Homework recent

ECET 105 Week 7 Homework recent

1. Sketch the Q output for the waveforms shown. Assume that Q starts LOW.
2. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.
3. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.
4. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.
5. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.
6. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.
7. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.
8. Sketch the Q0 and Q1 outputs for the circuit shown below. Assume that both Q0 and Q1 start LOW.
9. What is the output frequency for Q1 in the circuit shown below?
10. What is the output frequency for Q2 in the circuit shown below?

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ECET 105 Week 6 iLab Decoders and Multiplexers recent

ECET 105 Week 6 iLab Decoders and Multiplexers recent

Objectives:
To learn about the operation of a BCD-to-seven-segment decoder
To learn about the operation of a seven-segment display
To learn about the operation of multiplexers
To build and test a multiplexed display circuit using both discrete components and the eSOC III board
Questions:
Why are the 330 Ω resistors required for the discrete logic circuit, but not for the MultiSim simulated circuit or the eSOC III circuit?
Create a partial truth table showing the requirements for a seven-segment decoder to output a hexadecimal digit. This requires four input bits and six output states, A – F. For each output state, show the segments a-g. The output states for the inputs 0 – 9 are the same as for the 74LS47 (see focus.ti.com). Use capital letters A, C, E, F and lower case for b and d.
Why is the seven-segment display driven with an active-LOW signal using discrete logic and an active-HIGH with the eSOC board?

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ECET 105 Week 6 Homework recent

ECET 105 Week 6 Homework recent

1. When a HIGH is on the output of the decoding circuit below, what is the binary code appearing on the inputs?
2. Write the Boolean equations for each of the following codes if an active-LOW decoder output is required. The first decode is shown as an example.
3. What are the active outputs of a BCD-to-7 segment decoder with an input of 0100?
4. A 7-segment decoder/driver drives the display below. Using the waveforms shown, determine the sequence of digits that appear on the display.
5. Construct a truth table for an active-LOW output BCD (1-of-10) decoder.
6. Derive the truth table for the Y output in the diagram below.
7. Derive the Boolean equation for the Y output in Problem 6.
8. For the multiplexer shown below, determine the output for the following input state.
D0 = 0, D1 = 1, D2 = 1, D3 = 0, S0 = 1, S1 = 0.
9. Determine the function of the circuit shown below.
10. Write the Boolean equation for the circuit shown in Problem 9.

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ECET 105 Week 5 iLab Designing Adders and Subtractors recent

ECET 105 Week 5 iLab Designing Adders and Subtractors recent

Objectives:
The objectives are to reinforce the concepts of binary addition/subtraction while using the Quartus II Programmable Logic Tool as well as getting used to the program.  We were also supposed to build and test a simple adder/subtractor using the eSOC III Board.
Observations/Measurements:
Describe any problems you had with this week’s assignment.
1. In the simulation run of the four-bit adder, when we performed the addition 5 + 3, we did not immediately have an output of 8 on SOUT. What could be the cause of this?
2. If we changed the count period to 1000 nS for A and B, would this correct the anomalies in Question 1? Why or why not?
3. How fast can your 4-bit adder/subtractor determine the sum or difference of two numbers?
4. Use the simulation timing diagram to compare the worst case time to do an operation with your adder/subtractor with the worst case using the 74LS283. State which operation takes the longest and list the time required for both devices.

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ECET 105 Week 5 Homework recent

ECET 105 Week 5 Homework recent

1. Determine the decimal value of each of the following unsigned binary numbers:
2. Determine the decimal value of each of the following signed binary numbers displayed in the 2’s complement form:
3. Determine the outputs (Cout, Sout) of a full-adder for each of the following inputs:
4. The circuit below is an attempt to build a half-adder. Will the Cout and Sout function properly? Demonstrate your rationale.
5. Determine the outputs for the circuit shown below. Assume that C0 = 0 for all cases.
6. Derive the Boolean equation for A = B, when A and B are 4-bit numbers.
7. Complete the timing diagram below for a 2-bit adder. (10 points)
8. Answer the following:
What is the frequency of a periodic waveform with a period of 1.0 µsec?
How many bits are required to represent decimal numbers from -256 to +255?
What is the largest positive number that can be represented by 10 signed bits?
9. The full-adder shown below is tested under all input conditions as shown. Is the circuit operating correctly? If not, what is the most likely fault?
10. Using a 4-bit adder/subtractor, carry out the binary operations for 9 – 3 and 3 – 9. What can you conclude about the answers and the carry out bit (C4)?

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ECET 105 Week 4 iLab Logic Circuit Design, Simplification, Simulation, and Verification recent

ECET 105 Week 4 iLab Logic Circuit Design, Simplification, Simulation, and Verification recent

Objectives:
To design a digital logic circuit using a truth table and sum-of-product (SOP) formulation.
To use the MultiSim program to simplify, simulate, and test the circuit operation.
To build and test the logic circuit to verify that the system performs as expected.
Results:
Built a circuit board which would turn on the LED light and used multisim and tools which would simplify to do so. Verified the truth table to check and see if the vales are accurate.

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ECET 105 Week 4 Homework recent

ECET 105 Week 4 Homework recent

1. Draw a logic circuit that performs the following Boolean expression:
2. Determine the Boolean expression for the circuit shown below.
3. The Boolean expression for an AND gate is . Does the expression also describe an AND gate? Prove your answer.
4. Write the Boolean expression for the logic circuit shown below.
5. Develop the truth table for the circuit shown in Problem 4.
6. Develop the truth table for the circuit shown below.
7. Develop the Boolean expression for the circuit shown in Problem 6.
8. Draw a logic circuit using only NAND gates to implement the following Boolean expression: Y =AB + C.
9. Develop a logic circuit, using only NAND gates, to implement a circuit to meet the requirements of the truth table shown below.
10. Determine the Boolean description for the circuit shown below.

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